The present invention relates to memory controllers which produce row address strobe (RAS) signals from addresses produced by a microprocessor in order to select an appropriate bank of memory.
In a typical personal computer, a number of semiconductor chips are needed to assist the microprocessor in various functions. A memory controller chip is often used to control dynamic random access memory (DRAM). Typically, the microprocessor will simply generate addresses on a group of address lines. The memory controller decodes these addresses and determines which of a number of banks of memory to select. This is typically done by decoding the higher order address bits, while the lower order address bits are provided directly to the memory chips in the bank to select the appropriate location in the particular bank of memory.
Such a memory controller is also used to refresh the DRAM. DRAM memory must periodically have signals applied to each of its memory locations to maintain the charge which indicates stored data. This is called a refresh operation and requires periodically selecting address locations for refresh.
The memory controller chip has a limited number of pins. In addition to the functions described above, it performs many other functions as well. In a typical memory configuration, four output pins might be dedicated as the RAS outputs for selecting one of four banks of memory. If a typical PC maker wants to use 10 banks of memory, for instance, 10 RAS outputs would be required. This obviously would require more pins on the memory controller semiconductor chip, or require eliminating other functions provided by the MMU. In addition, providing several different types of physically different chips depending upon the number of banks of memory a PC maker will want to implement would be very costly.
One possibility would be to do the address decoding necessary to generate the RAS signals outside of the memory controller, by bypassing the memory controller and using the addresses from the microprocessor directly. However, this solution does not allow addresses which are translated by the memory controller to be used. For instance, many memory controllers support extended memory space (EMS). EMS provides a mapping from one address space to another to provide additional memory space which would not be addressable by the number of address bits from the microprocessor itself This is accomplished by setting up an EMS window address, which, when addressed, activates a translation mechanism which provides a substitute, translated address. The memory controller, when EMS is activated, uses the EMS address to generate the RAS signals. A circuit external to the memory controller would not be able to have access to these EMS addresses unless more pins were used to output them from the memory controller chip.